(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a process used to create a borderless contact opening, to a salicide surface.
(2) Description of Prior Art
The semiconductor industry is continually striving to reduce the processing cost of a specific semiconductor chip, by reducing the size of the chip, while still maintaining, or increasing the device density of that specific semiconductor chip. The attainment of additional chips, from a specific size starting semiconductor substrate, reduces the processing cost of a specific chip. The attainment of smaller semiconductor chips has been in part a result of micro-miniaturization, or the ability to fabricate semiconductor chips using sub-micron features. Micro-miniaturization has been accomplished via advancements in specific semiconductor fabrication procedures, such as photolithography and reactive ion etching. More sophisticated exposure tools, and the development of more sensitive photoresist materials, have allowed sub-micron images to be routinely achieved in photoresist layers. In addition the development of advanced dry etching tools and processes, have allowed the sub-micron images, in masking photoresist layers, to be transferred to underlying materials, such a silicon oxide, silicon nitride, and polysilicon, creating these materials, with sub-micron features, this resulting in smaller semiconductor chips, still possessing higher device densities than counterparts fabricated using larger features.
However in addition to the contributions to the attainment of micro-miniaturization, offered by advances in fabrication disciplines, specific structural developments have also positively influenced the attainment of smaller, higher device density, semiconductor chips. The use of a borderless contact, or an opening not fully landed on the underlying material being exposed in the contact hole, has contributed to the pursuit of micro-miniaturization. If a fully landed contact opening were used, the ground rules, or design, insuring the attainment of a fully landed contact opening, would adversely influence device density, therefore the borderless, or not fully landed contact hole, approach is used. Since the borderless contact opening will expose an underlying, material, such as an insulator, as well as exposing the desired underlying material, such as a conductive region of an active device region, special care most be used during the reactive ion etching, (RIE), procedure, used to open the borderless contact, in terms of selectivity to both materials. Therefore thin etch stop layers, such as silicon nitride, are used to allow monitoring of the RIE procedure, allowing a first phase of the RIE the procedure, used to create an opening in a silicon oxide layer, to slow or terminate at the appearance of the silicon nitride layer. A second phase of the RIE procedure is than used that will selectively remove the silicon nitride stop layer, without attacking insulator material, such as silicon oxide, exposed along with silicon, or metal silicide material, at the bottom of the borderless contact opening.
A critical problem encountered however, is the combination of silicon nitride stop layers, overlying metal silicide layers, such as titanium silicide, located on the surface of active device regions. The use of silicon nitride layers, formed in a furnace at a temperatures greater than about 650.degree. C., can result in a metal silicide agglomeration phenomena, changing the continuos metal silicide layer to a layer comprised with masses or balls of the metal silicide, resulting in significant increases in metal silicide resistance, thus adversely influencing device performance. This invention will describe a borderless contact process, using a silicon oxynitride layer, as a stop layer, for the first phase of the RIE procedure, used the borderless contact. The silicon oxynitride layer, obtained via chemical vapor deposition procedures, at a temperature of about 350.degree. C., will offer the desired RIE etch selectively, without initiating metal silicide agglomeration, thus maintaining low metal silicide resistance. Prior art, such a Jang et al, in U.S. Pat. No. 5,840,624, offer a borderless contact procedure, however that prior art does not open borderless contacts to metal silicide layers, therefore metal silicide agglomeration is not a concern, in addition to that prior art not using the novel, low temperature silicon oxynitride etch stop layer, overlying a metal silicide layer.